MAX 7000 Programmable Logic Device Family Data Sheet
Table 18. MAX 7000 & MAX 7000E External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
MAX 7000E (-10P) MAX 7000 (-10)
MAX 7000E (-10)
Min
Max
Min
Max
tPD1
tPD2
tSU
Input to non-registered output
I/O input to non-registered output
Global clock setup time
C1 = 35 pF
C1 = 35 pF
10.0
10.0
10.0
10.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.0
0.0
3.0
0.5
8.0
0.0
3.0
0.5
tH
Global clock hold time
tFSU
tFH
tCO1
tCH
Global clock setup time of fast input (2)
Global clock hold time of fast input (2)
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
5.0
5
4.0
4.0
2.0
3.0
4.0
4.0
3.0
3.0
tCL
tASU
tAH
tACO1
tACH
tACL
tCPPW
C1 = 35 pF
10.0
10.0
4.0
4.0
4.0
4.0
4.0
4.0
Minimum pulse width for clear and (3)
preset
tODH
tCNT
fCNT
Output data hold time after clock
Minimum global clock period
C1 = 35 pF (4)
1.0
1.0
ns
ns
10.0
10.0
10.0
10.0
Maximum internal global clock
frequency
(5)
100.0
100.0
MHz
tACNT
fACNT
Minimum array clock period
ns
Maximum internal array clock
frequency
(5)
(6)
100.0
125.0
100.0
125.0
MHz
fMAX
Maximum clock frequency
MHz
30
Altera Corporation
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