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EPM7192SQC160-10 参数 Datasheet PDF下载

EPM7192SQC160-10图片预览
型号: EPM7192SQC160-10
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件输入元件LTE时钟
文件页数/大小: 62 页 / 1087 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 7000 Programmable Logic Device Family Data Sheet  
Tables 16 through 23 show the MAX 7000 and MAX 7000E AC operating  
conditions.  
Table 16. MAX 7000 & MAX 7000E External Timing Parameters  
Note (1)  
Symbol  
Parameter  
Conditions  
-6 Speed Grade  
-7 Speed Grade  
Unit  
Min  
Max  
Min  
Max  
tPD1  
tPD2  
tSU  
Input to non-registered output  
I/O input to non-registered output  
Global clock setup time  
C1 = 35 pF  
C1 = 35 pF  
6.0  
6.0  
7.5  
7.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
5.0  
0.0  
2.5  
0.5  
6.0  
0.0  
3.0  
0.5  
tH  
Global clock hold time  
tFSU  
tFH  
tCO1  
tCH  
Global clock setup time of fast input (2)  
Global clock hold time of fast input  
Global clock to output delay  
Global clock high time  
Global clock low time  
(2)  
C1 = 35 pF  
4.0  
6.5  
4.5  
7.5  
2.5  
2.5  
2.5  
2.0  
3.0  
3.0  
3.0  
2.0  
tCL  
tASU  
tAH  
Array clock setup time  
Array clock hold time  
tACO1  
tACH  
tACL  
tCPPW  
Array clock to output delay  
Array clock high time  
C1 = 35 pF  
3.0  
3.0  
3.0  
3.0  
3.0  
3.0  
Array clock low time  
Minimum pulse width for clear and  
preset  
(3)  
tODH  
tCNT  
fCNT  
Output data hold time after clock  
Minimum global clock period  
C1 = 35 pF (4)  
1.0  
1.0  
ns  
ns  
6.6  
6.6  
8.0  
8.0  
Maximum internal global clock  
frequency  
(5)  
151.5  
125.0  
MHz  
tACNT  
fACNT  
Minimum array clock period  
ns  
Maximum internal array clock  
frequency  
(5)  
(6)  
151.5  
200  
125.0  
166.7  
MHz  
fMAX  
Maximum clock frequency  
MHz  
28  
Altera Corporation  
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