MAX 7000 Programmable Logic Device Family Data Sheet
Figure 13. Switching Waveforms
tR & tF < 3 ns.
Combinatorial Mode
Inputs are driven at 3 V
for a logic high and 0 V
for a logic low. All timing
characteristics are
tIN
Input Pin
I/O Pin
tIO
measured at 1.5 V.
tPIA
PIA Delay
tSEXP
Shared Expander
Delay
tLAC , tLAD
Logic Array
Input
tPEXP
Parallel Expander
Delay
tCOMB
Logic Array
Output
tOD
Output Pin
Global Clock Mode
tR
tCH
tCL
tF
Global
Clock Pin
tIN
tGLOB
Global Clock
at Register
tSU
tH
Data or Enable
(Logic Array Output)
Array Clock Mode
tR
tACH
tACL
tF
Input or I/O Pin
Clock into PIA
tIN
tIO
tPIA
Clock into
Logic Array
tIC
tSU
Clock at
Register
tH
Data from
Logic Array
tRD
tPIA
tPIA
tCLR , tPRE
Register to PIA
to Logic Array
tOD
tOD
Register Output
to Pin
Altera Corporation
27
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