欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM7192SQC160-10 参数 Datasheet PDF下载

EPM7192SQC160-10图片预览
型号: EPM7192SQC160-10
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件输入元件LTE时钟
文件页数/大小: 62 页 / 1087 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EPM7192SQC160-10的Datasheet PDF文件第23页浏览型号EPM7192SQC160-10的Datasheet PDF文件第24页浏览型号EPM7192SQC160-10的Datasheet PDF文件第25页浏览型号EPM7192SQC160-10的Datasheet PDF文件第26页浏览型号EPM7192SQC160-10的Datasheet PDF文件第28页浏览型号EPM7192SQC160-10的Datasheet PDF文件第29页浏览型号EPM7192SQC160-10的Datasheet PDF文件第30页浏览型号EPM7192SQC160-10的Datasheet PDF文件第31页  
MAX 7000 Programmable Logic Device Family Data Sheet  
Figure 13. Switching Waveforms  
tR & tF < 3 ns.  
Combinatorial Mode  
Inputs are driven at 3 V  
for a logic high and 0 V  
for a logic low. All timing  
characteristics are  
tIN  
Input Pin  
I/O Pin  
tIO  
measured at 1.5 V.  
tPIA  
PIA Delay  
tSEXP  
Shared Expander  
Delay  
tLAC , tLAD  
Logic Array  
Input  
tPEXP  
Parallel Expander  
Delay  
tCOMB  
Logic Array  
Output  
tOD  
Output Pin  
Global Clock Mode  
tR  
tCH  
tCL  
tF  
Global  
Clock Pin  
tIN  
tGLOB  
Global Clock  
at Register  
tSU  
tH  
Data or Enable  
(Logic Array Output)  
Array Clock Mode  
tR  
tACH  
tACL  
tF  
Input or I/O Pin  
Clock into PIA  
tIN  
tIO  
tPIA  
Clock into  
Logic Array  
tIC  
tSU  
Clock at  
Register  
tH  
Data from  
Logic Array  
tRD  
tPIA  
tPIA  
tCLR , tPRE  
Register to PIA  
to Logic Array  
tOD  
tOD  
Register Output  
to Pin  
Altera Corporation  
27  
 复制成功!