MAX 7000 Programmable Logic Device Family Data Sheet
Figure 12. MAX 7000 Timing Model
Internal Output
Enable Delay
t
IOE (1)
Global Control
Delay
Input
Delay
t I N
Output
Delay
tGLOB
Register
Delay
tSU
Parallel
Expander Delay
tPEXP
Logic Array
Delay
t LAD
tOD1
PIA
Delay
tPIA
tH
t
OD2 (2)
tOD3
tXZ
tPRE
tCLR
tRD
Register
tZX1
Control Delay
tCOMB
tFSU
tFH
t
t
ZX2 (2)
ZX3 (1)
tLAC
tIC
tEN
I/O
Delay
tIO
Shared
Expander Delay
tSEXP
Fast
Input Delay
tFIN
(1)
Notes:
(1) Only available in MAX 7000E and MAX 7000S devices.
(2) Not available in 44-pin devices.
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Figure 13 shows the internal timing
relationship of internal and external delay parameters.
For more infomration, see Application Note 94 (Understanding MAX 7000
Timing).
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Altera Corporation
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