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EPM7192SQC160-10 参数 Datasheet PDF下载

EPM7192SQC160-10图片预览
型号: EPM7192SQC160-10
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件输入元件LTE时钟
文件页数/大小: 62 页 / 1087 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 7000 Programmable Logic Device Family Data Sheet  
Table 22. MAX 7000 & MAX 7000E External Timing Parameters  
Note (1)  
Symbol  
Parameter  
Conditions  
Speed Grade  
-15T  
Min Max Min Max Min Max  
Unit  
-15  
-20  
tPD1  
tPD2  
Input to non-registered output C1 = 35 pF  
15.0  
15.0  
15.0  
15.0  
20.0  
20.0  
ns  
ns  
I/O input to non-registered  
output  
C1 = 35 pF  
tSU  
tH  
Global clock setup time  
Global clock hold time  
11.0  
0.0  
11.0  
0.0  
12.0  
0.0  
ns  
ns  
ns  
tFSU  
Global clock setup time of fast (2)  
3.0  
5.0  
input  
tFH  
Global clock hold time of fast  
input  
(2)  
0.0  
0.0  
ns  
tCO1  
tCH  
Global clock to output delay  
Global clock high time  
Global clock low time  
Array clock setup time  
Array clock hold time  
Array clock to output delay  
Array clock high time  
Array clock low time  
C1 = 35 pF  
8.0  
8.0  
12.0  
20.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
5.0  
5.0  
4.0  
4.0  
6.0  
6.0  
4.0  
4.0  
6.0  
6.0  
5.0  
5.0  
tCL  
tASU  
tAH  
tACO1  
tACH  
tACL  
tCPPW  
C1 = 35 pF  
15.0  
15.0  
6.0  
6.0  
6.0  
6.5  
6.5  
6.5  
8.0  
8.0  
8.0  
Minimum pulse width for clear (3)  
and preset  
tODH  
Output data hold time after  
clock  
C1 = 35 pF (4)  
1.0  
1.0  
1.0  
ns  
tCNT  
fCNT  
Minimum global clock period  
13.0  
13.0  
13.0  
13.0  
16.0  
16.0  
ns  
Maximum internal global clock (5)  
frequency  
76.9  
76.9  
62.5  
MHz  
tACNT  
fACNT  
Minimum array clock period  
ns  
Maximum internal array clock (5)  
frequency  
76.9  
100  
76.9  
83.3  
62.5  
83.3  
MHz  
fMAX  
Maximum clock frequency  
(6)  
MHz  
34  
Altera Corporation  
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