MAX 7000 Programmable Logic Device Family Data Sheet
Table 17. MAX 7000 & MAX 7000E Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade -6 Speed Grade -7
Unit
Min
Max
Min
Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.4
0.4
0.8
3.5
0.8
2.0
2.0
0.5
0.5
1.0
4.0
0.8
3.0
3.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tFIN
(2)
tSEXP
tPEXP
tLAD
tLAC
tIOE
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
(2)
tOD1
Output buffer and pad delay
Slow slew rate = off, VCCIO = 5.0 V
C1 = 35 pF
2.0
2.5
7.0
tOD2
tOD3
Output buffer and pad delay
Slow slew rate = off, VCCIO = 3.3 V
C1 = 35 pF (7)
C1 = 35 pF (2)
2.5
7.0
ns
ns
Output buffer and pad delay
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
tZX1
tZX2
tZX3
Output buffer enable delay
Slow slew rate = off, VCCIO = 5.0 V
C1 = 35 pF
4.0
4.5
9.0
4.0
4.5
9.0
ns
ns
ns
Output buffer enable delay
Slow slew rate = off, VCCIO = 3.3 V
C1 = 35 pF (7)
C1 = 35 pF (2)
Output buffer enable delay
Slow slew rate = on
VCCIO = 5.0 V or 3.3 V
tXZ
Output buffer disable delay
Register setup time
Register hold time
C1 = 5 pF
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSU
3.0
1.5
2.5
0.5
3.0
2.0
3.0
0.5
tH
tFSU
tFH
Register setup time of fast input
Register hold time of fast input
Register delay
(2)
(2)
tRD
0.8
0.8
2.5
2.0
0.8
2.0
2.0
0.8
10.0
1.0
1.0
3.0
3.0
1.0
2.0
2.0
1.0
10.0
tCOMB
tIC
Combinatorial delay
Array clock delay
tEN
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
tGLOB
tPRE
tCLR
tPIA
tLPA
Low-power adder
(8)
Altera Corporation
29
ALTERA [ ALTERA CORPORATION ]
