Chapter 15: Using the Agilent 3070 Tester for In-System Programming
15–7
Agilent 3070 Development Flow without the PLD ISP Software
Keep the test execution in the same order in which the SVF File was split. For
example, if the SVF File was split into four files (pcf1, pcf2, pcf3, and pcf4), the tests
must be executed in the order that they split (execute prog_afollowed by prog_b
followed by prog_cfollowed by prog_d). If the order is not preserved, the device(s)
will fail to program correctly.
Step 5: Compile the Executable Tests
Altera recommends batch-driven compilation using either BT-Basic or a UNIX shell.
See the following batch file code in BT-Basic (assuming four executable tests to
program the target device and generation of debugging object code):
compile "digital/prog_a" ; debug
compile "digital/prog_b" ; debug
compile "digital/prog_c" ; debug
compile "digital/prog_d" ; debug
This file should be saved in the board directory to allow engineering changes to take
place at a later date. See the corresponding shell script (–D option generates
debugging information):
dcomp -D digital/prog_a
dcomp -D digital/prog_b
dcomp -D digital/prog_c
dcomp -D digital/prog_d
1
Compile times can be long, depending on the number of PCF vectors contained in the
source files, the type of controller, and controller loading. Altera recommends using a
batch file to automate the compilation of the ISP tests.
If a boundary-scan chain containing Altera devices is defined, only the Altera devices
will be programmed when the PCF vectors have been applied to the JTAG interface.
Step 6: Debug the Test
Once the executable tests have been created, the test system can be debugged. The
applied vector set ensures that the device is programmed correctly by verifying the
contents of the device. The programming algorithm uses the TDOpin to check the
bitstream coming from the device. If any vector does not match the expected value,
the test fails, indicating one of two things:
■
The device ID does not match what is expected. This scenario is evident if the
failure occurs at the beginning of the first test.
■
Device programming failed.
Because many vectors are verified, it may not be practical to sift through each vector
to determine the cause of the failure. Use the following troubleshooting guidelines if
the device fails to program:
■
Check the pull-down resistor in the test fixture. The design engineer may have
placed pull-up resistors on the board for the TCKpin. If the pull-down resistor is
too large, the TCKpin may be above the device’s threshold for a logic low. Adjust
the value of the resistor accordingly. See the appropriate device family data sheet
for the specification on input logic levels.
© October 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
