15–10
Chapter 15: Using the Agilent 3070 Tester for In-System Programming
Programming Times
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Execution time for larger CPLDs and configuration devices is faster as only a
single digital test file is executed.
With Agilent’s PLD ISP software, a Jam Byte-Code Player is implemented in the
Control XTP card of the tester. This allows users to program devices using JBC files
created directly from Quartus II. The tester also supports Jam or SVF files as it has a
JBC compiler to compile these files for programming. The Jam Byte-Code Player is
executed via the microcontroller on the Control XTP card and allows users to apply
vectors algorithmically rather than executing a sequence of vectors. The Jam Byte-
Code Player reads the programming and erase pulse width registers of the devices
and uses those values in the programming and erase algorithms.
Programming Times
Programming times on the Agilent 3070 are very consistent. The only variable is the
TCKfrequency, which affects programming times. The faster the clock, the less time is
spent shifting data into the device. The programming time is a function of the TCK
clock rate. MAX II devices support TCKclock rates up to 18 MHz.
Guidelines
While using the Agilent 3070 tester for programming, use the following guidelines:
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Use caution if a pin library is used to describe the target device in a stand-alone
boundary-scan chain. Altera does not recommend describing all of the ISP
device’s I/O pins as bidirectional. This practice uses a large number of hybrid card
channels and potentially causes a fixture overflow error when developing the test.
■
Do not include PCF vectors in the test library. Use a setup-only node library.
Creating a test library with PCF vectors creates a large library object file and
results in a much slower test development time. This delay occurs because the
integrated program generator (IPG) looks at the entire vector set of the library
object to determine if vectors need to be commented out due to conflicts. Library
object compiles are different from executable compiles. Additionally, the IPG may
fail due to the large library object file.
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To save time and disk space, generate SVF Files that include a verify in the
programming operation. This process integrates verification vectors into one step,
minimizing the amount of work in the test development process. This integrated
verify accurately captures any programming errors; therefore, it is not necessary to
add an additional stand-alone verify in the test sequence.
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While this document describes how to generate a test to apply vectors to the
device for programming, a boundary-scan description language (BSDL) file is
required to functionally test the device. If you need to perform a boundary-scan
test or functional test, generate a BSDL file for the programmed state of the target
device that contains the pin configuration information (for example, which pins
are inputs, outputs, or bidirectional pins). Use the Agilent 3070 boundary-scan
software to generate a test.
f
For more information about Altera’s support for boundary-scan testing, refer to the
IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices chapter in the MAX II
Device Handbook.
MAX II Device Handbook
© October 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
