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EPM240T100C5 参数 Datasheet PDF下载

EPM240T100C5图片预览
型号: EPM240T100C5
PDF下载: 下载PDF文件 查看货源
内容描述: [最大II器件]
分类和应用: 可编程逻辑器件输入元件PC
文件页数/大小: 295 页 / 3815 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 15: Using the Agilent 3070 Tester for In-System Programming  
15–3  
Agilent 3070 Development Flow without the PLD ISP Software  
Step 1: Create a PCB and Test Fixture  
Before starting test development, the first step to successful in-system programming  
is the proper layout of the board and the subsequent creation of the test fixture.  
Creating the PCB  
The following recommendations highlight important areas of PCB design issues:  
The TCKsignal trace should be treated as carefully as a clock tree. TCKis the clock  
for the entire Joint Test Action Group (JTAG) chain of devices. These devices are  
edge-triggered on the TCKsignal, so it is imperative that this signal be protected  
from high-frequency noise and have good signal integrity. Ensure that the signal  
meets the tR and tF parameters specified in the device data sheet.  
Add a pull-down resistor to TCK. The TCKsignal should be held low through a  
pull-down resistor in-between PCF downloads. For more information about  
pattern capture format (PCF) downloads, refer to “Step 2: Create a Serial Vector  
Format File”. You should hold TCKlow because the Agilent 3070 drivers go into a  
“high-Z” state in-between tests and briefly drive low as the next PCF is applied.  
When the TCKline “floats”, the programming data stream is corrupted and the  
device is not programmed correctly.  
Provide VCCand GNDtest access points for the nails of the test fixture. During  
operation, there should be enough access points to allow quiet PCB operation.  
Having too few access points results in a noisy system that can disrupt JTAG  
scans.  
Turn off on-board oscillators. During programming, on-board oscillators should  
have the ability to be electrically turned off to reduce system noise.  
Add external resistors to pull outputs to a defined logic level during  
programming.  
1
Output pins are tri-stated during programming and are pulled up by a weak internal  
resistor. However, Altera recommends that signals requiring a pre-defined level be  
externally forced to the appropriate level using an external resistor.  
f
For more information about board design for ISP, refer to the In-System  
Programmability Guidelines for MAX II Devices chapter in the MAX II Device Handbook.  
Creating the Fixture  
Providing a clean interface between the test fixture and the target board is essential for  
successful in-system programming. To provide a clean interface, use short wires in the  
test fixture to improve the TCKconnection. Longer wires can introduce inductive  
noise into the system, which can disrupt programming. The wire connecting TCK  
should be no longer than 1 inch. Use the Agilent Fixture Consultant to manage the  
layout and creation of the test fixture (see the Agilent Board Test Family Manual).  
© October 2008 Altera Corporation  
MAX II Device Handbook  
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