9–34
Chapter 9: Using User Flash Memory in MAX II Devices
Software Support for UFM Block
5. nCSis pulled back to high to terminate the transmission.
Figure 9–36. WRSR Operation Sequence
nCS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
SI
8-bit
Instruction
01H
Status Register In
MSB
MSB
High Impendance
SO
Table 9–12. Block Write Protect Bits for Extended Mode
Status Register Bits
UFM Array Address
Protected
Level
0 (No protection)
3 (Full protection)
BP1
0
BP0
0
None
1
1
000 to 1FF
Table 9–13. Block Write Protect Bits for Base Mode
Status Register Bits
UFM Array Address
Protected
Level
0 (No protection)
3 (Full protection)
BP1
0
BP0
0
None
1
1
000 to 0FF
ALTUFM SPI Timing Specification
Figure 9–37 shows the timing specification needed for the SPI Extended mode
(read/write). These nCStiming specifications do not apply to the SPI Extended read-
only mode nor any of the SPI Base modes. However, for the SPI Extended mode (read
only) and the SPI Base mode (both read only and read/write), the nCSsignal and SCK
are not allowed to toggle at the same time. Table 9–14 shows the timing parameters
which only apply to the SPI Extended mode (read/write).
Figure 9–37. SPI Timing Waveform
t
HNCSHIGH
nCS
SCK
t
t
NCS2SCK
SCK2NCS
MAX II Device Handbook
© October 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
