欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM240T100C5 参数 Datasheet PDF下载

EPM240T100C5图片预览
型号: EPM240T100C5
PDF下载: 下载PDF文件 查看货源
内容描述: [最大II器件]
分类和应用: 可编程逻辑器件输入元件PC
文件页数/大小: 295 页 / 3815 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EPM240T100C5的Datasheet PDF文件第164页浏览型号EPM240T100C5的Datasheet PDF文件第165页浏览型号EPM240T100C5的Datasheet PDF文件第166页浏览型号EPM240T100C5的Datasheet PDF文件第167页浏览型号EPM240T100C5的Datasheet PDF文件第169页浏览型号EPM240T100C5的Datasheet PDF文件第170页浏览型号EPM240T100C5的Datasheet PDF文件第171页浏览型号EPM240T100C5的Datasheet PDF文件第172页  
9–36  
Chapter 9: Using User Flash Memory in MAX II Devices  
Software Support for UFM Block  
Figure 9–39. Page 3 altufm MegaWizard Plug-In Manager (SPI)  
1
The UFM block’s internal oscillator is always running when the altufm_spi  
megafunction is instantiated for read/write interface. The UFM block’s internal  
oscillator is disabled when the altufm_spimegafunction is instantiated for read  
only interface.  
Parallel Interface  
This interface allows for parallel communication between the UFM block and outside  
logic. Once the READrequest, WRITErequest, or ERASErequest is asserted (active low  
assertion), the outside logic or device (such as a microcontroller) are free to continue  
their operation while the data in the UFM is retrieved, written, or erased. During this  
time, the nBUSYsignal is driven “low” to indicate that it is not available to respond to  
any further request. After the operation is complete, the nBUSYsignal is brought back  
to “high” to indicate that it is now available to service a new request. If it was the  
Read request, the DATA_VALIDis driven “high” to indicate that the data at the DOport  
is the valid data from the last read address.  
Asserting READ, WRITE, and ERASEat the same time is not allowed. Multiple requests  
are ignored and nothing is read from, written to, or erased in the UFM block. There is  
no support for sequential read and page write in the parallel interface. For both the  
read only and the read/write modes of the parallel interface, OSC_ENAis always  
asserted, enabling the internal oscillator. Table 9–15 summarizes the parallel interface  
pins and functions.  
MAX II Device Handbook  
© October 2008 Altera Corporation  
 复制成功!