Chapter 9: Using User Flash Memory in MAX II Devices
9–37
Software Support for UFM Block
Table 9–15. Parallel Interface Signals
Pin
DI[15:0]
Description
16-bit data Input
Function
Receive 16-bit data in parallel. You can select an optional width of 3 to
16 bits using the altufm megafunction.
DO[15:0]
16-bit data Output
Address Register
Transmit 16-bit data in parallel. You can select an optional width of 3 to
16 bits using the altufm megafunction.
ADDR[8:0]
Operation sequence refers to the data that is pointed to by the address
register. You can determine the address bus width using the altufm
megafunction.
nREAD
READInstruction Signal
WRITEInstruction Signal
ERASEInstruction Signal
Initiates a read sequence.
Initiates a write sequence.
nWRITE
nERASE
Initiates a SECTOR-ERASE sequence indicated by the MSB of the
ADDR[]port.
nBUSY
BUSYSignal
Driven low to notify that it is not available to respond to any further
request.
DATA_VALID
Data Valid
Driven high to indicate that the data at the DOport is the valid data from
the last read address for read request.
Even though the altufm megafunction allows you to select the address widths range
from 3 bits to 9 bits, the UFM block always expects full 9 bits width for the address
register. Therefore, the altufm megafunction will always pad the remaining LSB of the
address register with '0's if the register width selected is less than 9 bits. The address
register will point to sector 0 if the address received at the address register starts with
a '0'. The address register will point to sector 1 if the address received starts with a '1'.
Even though you can select an optional data register width of 3 to 16 bits using the
altufm megafunction, the UFM block always expects full 16 bits width for the data
register. Reading from the data register always proceeds from MSB to LSB. The altufm
megafunction always pads the remaining LSB of the data register with 1s if the user
selects a data width of less than 16-bits.
ALTUFM Parallel Interface Timing Specification
Figure 9–40 shows the timing specifications for the parallel interface. Table 9–16
parallel interface instruction signals. The nREAD, nWRITE, and nERASEsignals are
active low signals.
© October 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
