9–28
Chapter 9: Using User Flash Memory in MAX II Devices
Software Support for UFM Block
shows the
READ
operation sequence for Base mode.
Figure 9–27.
READ Operation for Base Mode
nCS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23
SCK
8-bit
Instruction
SI
MSB
03
H
MSB
High Impendance
SO
8-bit
Data Out 1
MSB
8-bit
Data Out 2
MSB
8-bit
Instruction
WRITE
WRITE
is the instruction for data transmission, where the data is written to the UFM
block. The targeted location in the UFM block that will be written must be in the
erased state (FFFF
H
) before initiating a
WRITE
operation. When data transfer is taking
place, the MSB is always the first bit to be transmitted or received.
nCS
must be driven
high before the instruction is executed internally. You may poll the nRDY bit in the
software status register for the completion of the internal self-timed
WRITE
cycle. For
SPI Extended mode, the
WRITE
operation is always done through the following
sequence, as shown in
1.
nCS
is pulled low to indicate the start of transmission.
2. An 8-bit
WRITE
opcode (00000010) is received from the master device. If internal
programming is in progress, the
WRITE
operation is ignored and not accepted.
3. A 16-bit address is received from the master device. The LSB of the address will be
received last. As the UFM block can take only nine bits of address maximum, the
first seven address bits received are discarded.
4. A check is carried out on the status register (see
to determine if the
WRITE
operation has been enabled, and the address is outside of the protected
region; otherwise, Step 5 is bypassed.
5. One word (16 bits) of data is transmitted to the slave device through
SI.
6.
nCS
is pulled back to high to indicate the end of transmission.
For SPI Base mode, the
WRITE
operation is always performed through the following
sequence in SPI:
1.
nCS
is pulled low to indicate the start of transmission.
2. An 8-bit
WRITE
opcode (00000010) is received. If the internal programming is in
progress, the
WRITE
operation is ignored and not accepted.
3. An 8-bit address is received. A check is carried out on the status register (see
to determine if the
WRITE
operation has been enabled, and the address
is outside of the protected region; otherwise, Step 4 is skipped.
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