9–32
Chapter 9: Using User Flash Memory in MAX II Devices
Software Support for UFM Block
Figure 9–33.
WREN Operation Sequence
nCS
0
1
2
3
4
5 6 7
SCK
8-bit
Instruction
SI
MSB
High Impendance
06
H
SO
WRDI (Write Disable)
After the UFM is programmed,
WRDI
can be issued to set
WEN
back to
0,
disabling
WRITE
and preventing inadvertent writing to the UFM.
WRDI
is issued through the
following sequence, as shown in
1.
nCS
is pulled low.
2. Opcode
00000100
is transmitted to set
WEN
to
0
in the status register.
3. After the transmission of the eighth bit of
WRDI,
the interface is in wait state
(waiting for
nCS
to be pulled back to high). Any transmission after this is ignored.
4.
nCS
is pulled back to high.
Figure 9–34.
WRDI Operation Sequence
nCS
0
1
2
3
4
5 6 7
SCK
8-bit
Instruction
SI
MSB
High Impendance
04
H
SO
RDSR (Read Status Register)
The content of the status register can be read by issuing
RDSR.
Once
RDSR
is received,
the interface outputs the content of the status register through the
SO
port. Although
the most significant four bits (Bit 7 to Bit 4) do not hold valuable information, all eight
bits in the status register will output through the
SO
port. This allows future
compatibility when Bit 7 to Bit 4 have new meaning in the status register. During the
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