Chapter 9: Using User Flash Memory in MAX II Devices
Software Support for UFM Block
9–25
Table 9–9.
SPI Interface Signals
Pin
SI
SO
SCK
nCS
Description
Serial Data Input
Serial Data Output
Serial Data Clock
Chip Select
Receive data serially.
Transmit data serially.
The clock signal produced from the master device to
synchronize the data transfer.
Active low signal that enables the slave device to
receive or transfer data from the master device.
Function
Data transmitted to the
SI
port of the slave device is sampled by the slave device at
the positive
SCK
clock. Data transmits from the slave device through
SO
at the
negative
SCK
clock edge. When
nCS
is asserted, it means the current device is being
selected by the master device from the other end of the SPI bus for service. When
nCS
is not asserted, the
SI
and
SCK
ports should be blocked from receiving signals from
the master device, and
SO
should be in High Impedance state to avoid causing
contention on the shared SPI bus. All instructions, addresses, and data are transferred
with the MSB first and start with high-to-low
nCS
transition. The circuit diagram is
shown in
Figure 9–25.
Circuit Diagram for SPI Interface Read or Write Operations
SI SO SCK nCS
Op-Code Decoder
Read, Write, and Erase
State Machine
UFM Block
Address and Data Hub
SPI Interface
Control Logic
Eight-Bit Status Shift Register
Opcodes
The 8-bit instruction opcode is shown in
After
nCS
is pulled low, the
indicated opcode must be provided. Otherwise, the interface assumes that the master
device has internal logic errors and ignores the rest of the incoming signals. Once
nCS
is pulled back to high, the interface is back to normal.
nCS
should be pulled low again
for a new service request.
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