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EPM1270GT144I4N 参数 Datasheet PDF下载

EPM1270GT144I4N图片预览
型号: EPM1270GT144I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.1ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 108 页 / 1342 K
品牌: ALTERA [ ALTERA CORPORATION ]
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JTAG and In-System Programmability  
The MAX II device instruction register length is 10 bits and the USERCODE  
register length is 32 bits. Tables 3–2 and 3–3 show the boundary-scan  
register length and device IDCODEinformation for MAX II devices.  
Table 3–2. MAX II Boundary-Scan Register Length  
Device  
Boundary-Scan Register Length  
EPM240  
EPM570  
240  
480  
636  
816  
EPM1270  
EPM2210  
Table 3–3. 32-Bit MAX II Device IDCODE  
Binary IDCODE (32 Bits) (1)  
Device  
HEX IDCODE  
Version  
(4 Bits)  
Manufacturer  
Identity (11 Bits)  
LSB  
(1 Bit) (2)  
Part Number  
EPM240  
EPM240G  
0000  
0000  
0000  
0000  
0010 0000 1010 0001  
000 0110 1110  
000 0110 1110  
000 0110 1110  
000 0110 1110  
1
1
1
1
0x020A10DD  
0x020A20DD  
0x020A30DD  
0x020A40DD  
EPM570  
EPM570G  
0010 0000 1010 0010  
0010 0000 1010 0011  
0010 0000 1010 0100  
EPM1270  
EPM1270G  
EPM2210  
EPM2210G  
EPM240Z  
EPM570Z  
0000  
0000  
0010 0000 1010 0101  
0010 0000 1010 0110  
000 0110 1110  
000 0110 1110  
1
1
0x020A50DD  
0x020A60DD  
Notes to Table 3–2:  
(1) The most significant bit (MSB) is on the left.  
(2) The IDCODE’s least significant bit (LSB) is always 1.  
f
f
For JTAG AC characteristics, refer to the DC and Switching Characteristics  
chapter in the MAX II Device Handbook.  
For more information about JTAG BST, refer to the IEEE 1149.1 (JTAG)  
Boundary-Scan Testing for MAX II Devices chapter in the MAX II Device  
Handbook.  
Altera Corporation  
December 2007  
Core Version a.b.c variable  
3–3  
MAX II Device Handbook, Volume 1  
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