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EPM1270GT144I4N 参数 Datasheet PDF下载

EPM1270GT144I4N图片预览
型号: EPM1270GT144I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.1ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 108 页 / 1342 K
品牌: ALTERA [ ALTERA CORPORATION ]
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JTAG and In-System Programmability  
2. Check ID—Before any program or verify process, the silicon ID is  
checked. The time required to read this silicon ID is relatively small  
compared to the overall programming time.  
3. Sector Erase—Erasing the device in-system involves shifting in the  
instruction to erase the device and applying an erase pulse(s). The  
erase pulse is automatically generated internally by waiting in the  
run/test/idle state for the specified erase pulse time of 500 ms for  
the CFM block and 500 ms for each sector of the UFM block.  
4. Program—Programming the device in-system involves shifting in  
the address, data, and program instruction and generating the  
program pulse to program the flash cells. The program pulse is  
automatically generated internally by waiting in the run/test/idle  
state for the specified program pulse time of 75 µs. This process is  
repeated for each address in the CFM and UFM blocks.  
5. Verify—Verifying a MAX II device in-system involves shifting in  
addresses, applying the verify instruction to generate the read  
pulse, and shifting out the data for comparison. This process is  
repeated for each CFM and UFM address.  
6. Exit ISP—An exit ISP stage ensures that the I/O pins transition  
smoothly from ISP mode to user mode.  
Table 3–4 shows the programming times for MAX II devices using  
in-circuit testers to execute the algorithm vectors in hardware.  
Software-based programming tools used with download cables are  
slightly slower because of data processing and transfer limitations.  
Table 3–4. MAX II Device Family Programming Times  
EPM240 EPM570  
EPM1270  
EPM1270G EPM2210G  
EPM2210  
Description  
EPM240G  
EPM240Z  
EPM570G  
EPM570Z  
Unit  
Erase + Program (1 MHz)  
Erase + Program (10 MHz)  
Verify (1 MHz)  
1.72  
1.65  
0.09  
0.01  
1.81  
1.66  
2.16  
1.99  
0.17  
0.02  
2.33  
2.01  
2.90  
2.58  
0.30  
0.03  
3.20  
2.61  
3.92  
3.40  
0.49  
0.05  
4.41  
3.45  
sec  
sec  
sec  
sec  
sec  
sec  
Verify (10 MHz)  
Complete Program Cycle (1 MHz)  
Complete Program Cycle (10 MHz)  
Altera Corporation  
December 2007  
Core Version a.b.c variable  
3–7  
MAX II Device Handbook, Volume 1  
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