IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
JTAG Block
The MAX II JTAG block feature allows you to access the JTAG TAP and
state signals when either the USER0or USER1instruction is issued to the
JTAG TAP. The USER0and USER1instructions bring the JTAG
boundary-scan chain (TDI) through the user logic instead of the MAX II
device’s boundary-scan cells. Each USERinstruction allows for one
unique user-defined JTAG chain into the logic array.
Parallel Flash Loader
The JTAG block ability to interface JTAG to non-JTAG devices is ideal for
general-purpose flash memory devices (such as Intel- or Fujitsu-based
devices) that require programming during in-circuit test. The flash
memory devices can be used for FPGA configuration or be part of system
memory. In many cases, the MAX II device is already connected to these
devices as the configuration control logic between the FPGA and the flash
device. Unlike ISP-capable CPLD devices, bulk flash devices do not have
JTAG TAP pins or connections. For small flash devices, it is common to
use the serial JTAG scan chain of a connected device to program the
non-JTAG flash device. This is slow and inefficient in most cases and
impractical for large parallel flash devices. Using the MAX II device’s
JTAG block as a parallel flash loader, with the Quartus II software, to
program and verify flash contents provides a fast and cost-effective
means of in-circuit programming during test. Figure 3–1 shows MAX II
being used as a parallel flash loader.
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Core Version a.b.c variable
Altera Corporation
December 2007
MAX II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
