Timing Information
Figure 4–17. Read Operation Timing
nCS
t
CH
DCLK
t
nCLK2D
DATA
Bit
N
Bit
N
-
1
t
CL
Bit 0
t
ODIS
ASDI
Add_Bit 0
defines the serial configuration device timing parameters for
read operation.
Table 4–13. Read Operation Parameters
Symbol
f
RCLK
Parameter
Read clock frequency (from
FPGA or embedded processor)
for read bytes operation
Min
Max
20
Unit
MHz
t
CH
t
CL
t
ODIS
t
nCLK2D
DCLK
high time
DCLK
low time
Output disable time after read
Clock falling edge to data
25
25
15
15
ns
ns
ns
ns
4–26
Configuration Handbook, Volume 2
Core Version a.b.c variable
Altera Corporation
July 2004