Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Table 4–12 defines the serial configuration device timing parameters for
write operation.
Table 4–12. Write Operation Parameters
Symbol
Parameter
Min
Max
Unit
fWCLK
Write clock frequency (from
FPGA, download cable, or
embedded processor) for write
enable, write disable, read
status, read silicon ID, write
bytes, erase bulk, and erase
sector operations
25
MHz
tCH
20
20
10
10
5
ns
ns
ns
ns
ns
DCLKhigh time
tCL
DCLKlow time
tNCSSU
tNCSH
tDSU
Chip select (nCS) setup time
Chip select (nCS) hold time
Data (ASDI) in setup time
before rising edge on DCLK
tDH
5
ns
Data (ASDI) hold time after
rising edge on DCLK
tCSH
Chip select high time
100
2
ns
tWB_EPCS1 (1)
Write bytes cycle time for
EPCS1 devices
5
5
ms
tWB_EPCS4 (1)
Write bytes cycle time for
EPCS4 devices
1.5
ms
tWS (1)
Write status cycle time
5
3
15
6
ms
s
tEB_EPCS1 (1)
Erase bulk cycle time for
EPCS1 devices
tEB_EPCS4 (1)
tES (1)
Erase bulk cycle time for
EPCS4 devices
5
2
10
3
s
s
Erase sector cycle time
Note to Table 4–12:
(1) These parameters are not shown in Figure 4–16.
Figure 4–17 shows the timing waveform for the serial configuration
device's read operation.
Altera Corporation
July 2004
Core Version a.b.c variable
4–25
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
