Timing Information
parameter specifies the V
CC
supply current when the device is in active
power mode and the I
CC0
parameter specifies the current when the device
is in stand-by power mode (see
Power-On Reset
During initial power-up, a POR delay occurs to ensure the system voltage
levels have stabilized. During AS configuration, the FPGA controls the
configuration and has a longer POR delay than the serial configuration
device. Therefore, the POR delay is governed by the Stratix II FPGA
(typically 12 ms or 100 ms) or Cyclone series FPGA (typically 100 ms).
Error Detection
During AS configuration with the serial configuration device, the FPGA
monitors the configuration status through the
nSTATUS
and
CONF_DONE
pins. If an error condition occurs (nSTATUS drives low) or if the
CONF_DONE
pin does not go high, the FPGA will initiate reconfiguration
by pulsing the
nSTATUS
and
nCSO
signals, which controls the chip select
pin on the serial configuration device (nCS).
After an error, configuration automatically restarts if the
Auto-Restart
Upon Frame Error
option is turned on in the Quartus II software. If the
option is turned off, the system must monitor the
nSTATUS
signal for
errors and then pulse the
nCONFIG
signal low to restart configuration.
Timing
Information
shows the timing waveform for write operation to the serial
configuration device.
Figure 4–16. Write Operation Timing
t
CSH
nCS
t
NCSH
DCLK
t
DSU
ASDI
Bit
n
t
DH
Bit
n
-
1
Bit 0
t
NCSSU
t
CH
t
CL
DATA
High Impedance
4–24
Configuration Handbook, Volume 2
Core Version a.b.c variable
Altera Corporation
July 2004
ALTERA [ ALTERA CORPORATION ]
