Serial Configuration Device Memory Access
Write Bytes Operation
The write bytes operation code is b'0000 0010, with the MSB listed
first. The write bytes operation allows bytes to be written to the memory.
The write enable operation must be executed prior to the write bytes
operation to set the write enable latch bit in the status register to 1.
The write bytes operation is implemented by driving nCSlow, followed
by the write bytes operation code, three address bytes and a minimum
one data byte on ASDI. If the eight least significant address bits
(A[7..0]) are not all 0, all sent data that goes beyond the end of the
current page is not written into the next page. Instead, this data is written
at the start address of the same page (from the address whose eight LSBs
are all 0). Drive nCSlow during the entire write bytes operation sequence
as shown in Figure 4–13.
If more than 256 data bytes are shifted into the serial configuration device
with a write bytes operation, the previously latched data is discarded and
the last 256 bytes are written to the page. However, if less than 256 data
bytes are shifted into the serial configuration device, they are guaranteed
to be written at the specified addresses and the other bytes of the same
page are unaffected.
If the design must write more than 256 data bytes to the memory, it needs
more than one page of memory. Send the write enable and write bytes
operation codes followed by three new targeted address bytes and
256 data bytes before a new page is written.
nCSmust be driven high after the eighth bit of the last data byte has been
latched in. Otherwise, the device will not execute the write bytes
operation. The write enable latch bit in the status register is reset to 0
before the completion of each write bytes operation. Therefore, the write
enable operation must be carried out before the next write bytes
operation.
The device initiates the self-timed write cycle immediately after nCSis
driven high. The self-timed write cycle usually takes 1.5 ms for EPCS4
devices and 2 ms for EPCS1 devices and is guaranteed to be less than 5 ms
(see tWB in Table 4–12). Therefore, the designer must account for this
amount of delay before another page of memory is written. Alternatively,
the designer can check the status register’s write in progress bit by
executing the read status operation while the self-timed write cycle is in
progress. The write in progress bit is set to 1during the self-timed write
cycle, and is 0when it is complete.
4–20
Core Version a.b.c variable
Altera Corporation
July 2004
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
