Page 18
Timing Information
Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 2 of 2)
Symbol
tOEW
Parameter
OE low pulse width (reset) to guarantee counter reset
OE low (reset) to DCLKdisable delay
Min
100
—
Typ
—
—
—
Max
—
Units
ns
tOEC
20
ns
tNRCAS
OE low (reset) to nCASCdelay
—
25
ns
Note to Table 10:
(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.
Table 11 lists the timing parameters when using EPC1, EPC1064, EPC1064V, EPC1213,
and EPC1441 devices when configuring the FLEX 8000 device.
Table 11. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1064, EPC1064V, EPC1213, and EPC1441
Devices
EPC1064 and
EPC1213
EPC1 and
EPC1441
EPC1064V
Symbol
Parameter
Unit
Min
Max
75
Min
—
—
—
100
0
Max
50
50
50
—
—
—
—
75
—
6
Min
Max
50
50
50
—
—
—
—
75
—
8
tOEZX
OE high to DATAoutput enabled
—
—
—
—
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
tCSZX
tCSXZ
tCSS
tCSH
tDSU
tDH
n
n
n
n
CSlow to DATAoutput enabled
—
—
75
75
—
—
—
—
100
—
4
CS high to DATAoutput disabled
CSlow setup time to first DCLKrising edge
CSlow hold time after DCLKrising edge
150
0
Datasetup time before rising edge on DCLK
Datahold time after rising edge on DCLK
DCLKto DATAout delay
75
50
0
50
0
0
tCO
—
—
160
—
80
80
—
100
—
—
—
—
100
—
50
50
—
100
—
—
—
tCK
Clock period
240
—
fCK
Clock frequency
tCL
DCLKlow time
120
120
—
—
—
75
—
90
75
150
—
—
50
—
60
50
100
—
—
50
—
50
50
100
tCH
DCLKhigh time
tXZ
OE low or nCS high to DATAoutput disabled
OE pulse width to guarantee counter reset
Last DCLK+ 1 to nCASClow delay
Last DCLK+ 1 to DATAtri-state delay
tOEW
tCASC
tCKXZ
tCEOUT
150
—
—
nCShigh to nCASChigh delay
—
Configuration Devices for SRAM-Based LUT Devices
January 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
