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Timing Information
Timing Information
Figure 5 shows the timing waveform when using a configuration device.
Figure 5. Timing Waveform Using a Configuration Device
nINIT_CONF or VCC/nCONFIG
tPOR
OE/nSTATUS
nCS/CONF_DONE
tCH
tDSU
tCL
DCLK
DATA
tOEZX
tDH
D2
D0
D1
D3
Dn
(1)
tCO
User I/O
User Mode
Tri-State
Tri-State
INIT_DONE
Note to Figure 5:
(1) The EPC2 device drives DCLKlowand DATAhigh after configuration. The EPC1 and EPC1441 devices drive DCLKlow and tri-state DATAafter
configuration.
Table 8 lists the timing parameters when using EPC2 devices at 3.3 V.
Table 8. Timing Parameters when Using EPC2 devices at 3.3 V
Symbol
tPOR
tOEZX
tCE
tDSU
tDH
Parameter
Min
—
—
—
30
0
Typ
—
—
—
—
—
—
—
7.7
65
65
—
—
—
—
—
—
—
Max
200
80
Units
ms
ns
(1)
POR delay
OE high to DATAoutput enabled
OE high to first rising edge on DCLK
Datasetup time before rising edge on DCLK
Datahold time after rising edge on DCLK
DCLKto DATAout
300
—
ns
ns
—
ns
tCO
—
—
5
30
ns
tCDOE
fCLK
tMCH
tMCL
tSCH
tSCL
tCASC
tCCA
tOEW
tOEC
tNRCAS
DCLKto DATAenable/disable
30
ns
DCLKfrequency
12.5
100
100
—
MHz
ns
DCLKhigh time for the first device in the configuration chain
DCLKlow time for the first device in the configuration chain
DCLKhigh time for subsequent devices
DCLKlow time for subsequent devices
DCLKrising edge to nCASC
40
40
40
40
—
—
100
—
—
ns
ns
—
ns
25
ns
n
CSto nCASCcascade delay
15
ns
OE low pulse width (reset) to guarantee counter reset
OE low (reset) to DCLKdisable delay
OE low (reset) to nCASCdelay
—
ns
30
ns
30
ns
Note to Table 8:
(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.
Configuration Devices for SRAM-Based LUT Devices
January 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
