Timing Information
Page 17
Table 9 lists the timing parameters when using EPC1 and EPC1441 devices at 3.3 V.
Table 9. Timing Parameters when Using EPC1 and EPC1441 Devices at 3.3 V
Symbol Parameter
tPOR
tOEZX
tCE
tDSU
tDH
Min
—
—
—
30
0
Typ
—
—
—
—
—
—
—
4
Max
200
80
Units
ms
ns
(1)
POR delay
OE high to DATAoutput enabled
OE high to first rising edge on DCLK
Datasetup time before rising edge on DCLK
Datahold time after rising edge on DCLK
DCLKto DATAout
300
—
ns
ns
—
ns
tCO
—
—
2
30
ns
tCDOE
fCLK
tMCH
tMCL
tSCH
tSCL
tCASC
tCCA
tOEW
tOEC
tNRCAS
DCLKto DATAenable/disable
30
ns
DCLKfrequency
10
MHz
ns
DCLKhigh time for the first device in the configuration chain
DCLKlow time for the first device in the configuration chain
DCLKhigh time for subsequent devices
DCLKlow time for subsequent devices
DCLKrising edge to nCASC
50
50
50
50
—
—
100
—
—
125
125
—
—
—
—
—
—
—
250
250
—
ns
ns
—
ns
25
ns
nCSto nCASCcascade delay
15
ns
OE low pulse width (reset) to guarantee counter reset
OE low (reset) to DCLKdisable delay
OE low (reset) to nCASCdelay
—
ns
30
ns
30
ns
Note to Table 9:
(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.
Table 10 lists the timing parameters when using EPC1, EPC2, and EPC1441 devices at
5.0 V.
Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 1 of 2)
Symbol
tPOR
tOEZX
tCE
tDSU
tDH
Parameter
Min
—
—
—
30
0
Typ
—
—
—
—
—
—
—
10
50
50
—
—
—
—
Max
200
50
Units
ms
ns
(1)
POR delay
OE high to DATAoutput enabled
OE high to first rising edge on DCLK
Datasetup time before rising edge on DCLK
Datahold time after rising edge on DCLK
DCLKto DATAout
200
—
ns
ns
—
ns
tCO
—
—
6.7
30
30
30
30
—
—
20
ns
tCDOE
fCLK
tMCH
tMCL
tSCH
tSCL
tCASC
tCCA
DCLKto DATAenable/disable
20
ns
DCLKfrequency
16.7
75
MHz
ns
DCLKhigh time for the first device in the configuration chain
DCLKlow time for the first device in the configuration chain
DCLKhigh time for subsequent devices
DCLKlow time for subsequent devices
DCLKrising edge to nCASC
75
ns
—
ns
—
ns
20
ns
nCSto nCASCcascade delay
10
ns
January 2012 Altera Corporation
Configuration Devices for SRAM-Based LUT Devices
ALTERA [ ALTERA CORPORATION ]
