IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing
Page 15
Figure 4 shows the timing requirements for the JTAG signals.
Figure 4. EPC2 Device JTAG Waveforms
TMS
TDI
tJCP
tJCH
tJCL
tJPH
tJPSU
TCK
TDO
t
tJPXZ
tJPCO
JPZX
tJSSU
tJSH
Signal
to be
Captured
tJSZX
tJSCO
tJSXZ
Signal
to be
Driven
Table 7 lists the timing parameters and values for configuration devices.
Table 7. JTAG Timing Parameters and Values
Symbol
Parameter
Min
100
50
50
20
45
—
—
—
20
Max
—
—
—
—
—
25
25
25
—
—
25
25
25
Unit
tJCP
TCKclock period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCH
TCKclock high time
TCKclock low time
tJCL
tJPSU
tJPH
JTAG port setup time
JTAG port hold time
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
45
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
—
—
—
January 2012 Altera Corporation
Configuration Devices for SRAM-Based LUT Devices
ALTERA [ ALTERA CORPORATION ]
