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Pin Information
Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 2 of 3)
Pin Number
Pin Name
Pin Type
Description
8-Pin
20-Pin
PLCC
32-Pin
(1)
(2)
PDIP
TQFP
Chip select input (active low). The nCSpin connects to the
DONEpin of the FPGA.
CONF
_
A low input allows DCLKto increment the address counter
and enables DATAto drive out. If the EPC1 or EPC2 device
is reset (OEpulled low) while nCS is low, the device
initializes as the master device in a configuration chain. If
the EPC1 or EPC2 device is reset (OEpulled low) while nCS
is high, the device initializes as a slave device in the chain.
nCS
4
9
10
Input
The nCSpin has an internal programmable 1-k resistor
in EPC2 devices. If internal pull-up resistors are used, do
not use external pull-up resistors on these pins. You can
disable the internal pull-up resistors through the Disable
nCS and OE pull-ups on configuration device option.
Cascade select output (active low).
This output goes low when the address counter has
reached its maximum value. When the address counter has
reached its maximum value, the configuration device has
sent all its configuration data to the FPGA. In a chain of
EPC1 or EPC2 devices, the nCASCpin of one device is
connected to the nCSpin of the next device, which permits
DCLKto clock data from the next EPC1 or EPC2 device in
the chain. For single EPC1 or EPC2 device and the last
device in the chain, nCASC is left floating.
nCASC
6
12
15
Output
This pin is only available in EPC1 and EPC2 devices, which
support data cascading.
Allows the INIT
configuration. The nINIT
CONFIGpin of the FPGA.
_
CONFJTAG instruction to initiate
_CONFpin connects to the
n
If multiple EPC2 devices are used to configure an FPGA,
the nINIT CONFof the first EPC2 device pin is tied to the
FPGA’s nCONFIGpin, while subsequent devices'
INIT CONFpins are left floating.
_
Open-Drain
Output
nINIT
_
CONF
N/A
13
16
n
_
The INIT CONFpin has an internal 1-k pull-up resistor
_
that is always active in EPC2 devices.
This pin is only available in EPC2 devices.
JTAG data input pin. Connect this pin to VCC if the JTAG
circuitry is not used.
TDI
TDO
TMS
N/A
N/A
N/A
11
1
13
28
25
Input
This pin is only available in EPC2 devices.
JTAG data output pin. Do not connect this pin if the JTAG
circuitry is not used.
Output
Input
This pin is only available in EPC2 devices.
JTAG mode select pin. Connect this pin to VCC if the JTAG
circuitry is not used.
19
This pin is only available in EPC2 devices.
Configuration Devices for SRAM-Based LUT Devices
January 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
