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IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing
IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing
The EPC2 device provides JTAG BST circuitry that complies with the IEEE Std.
1149.1-1990 specification. You can perform JTAG BST before or after configuration, but
not during configuration. Table 6 lists the JTAG instructions supported by the EPC2
device.
Table 6. EPC2 Device JTAG Instructions
JTAG Instruction
OPCODE
Description
Allows a snapshot of a signal at the device pins to be captured and
examined during normal device operation and permits an initial data
pattern output at the device pins.
SAMPLE/PRELOAD
00 0101 0101
Allows the external circuitry and board-level interconnections to be
tested by forcing a test pattern at the output pins and capturing
results at the input pins.
EXTEST
BYPASS
00 0000 0000
11 1111 1111
Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through a selected
device to adjacent devices during normal device operation.
Selects the device IDCODEregister and places it between the TDI
and TDOpins, allowing the device IDCODEto be serially shifted out of
the TDOpin. The device IDCODEfor the EPC2 configuration device is
shown below:
IDCODE
00 0101 1001
00 0111 1001
0000 0001000000000010 00001101110 1
Selects the USERCODEregister and places it between the TDIand
TDOpins, allowing the USERCODEto be serially shifted out of the
TDO pin. The 32-bit USERCODEis a programmable user-defined
pattern.
USERCODE
Initiates the FPGA re-configuration process by pulsing the
nINIT_CONFpin low, which is connected to the FPGAs nCONFIG
pins. After this instruction is updated, the nINIT_CONFpin is pulsed
low when the JTAG state machine enters the Run-Test/Idle state. The
nINIT_CONFpin is then released and nCONFIGis pulled high by the
resistor after the JTAG state machine goes out of Run-Test/Idle state.
The FPGA configuration starts after the nCONFIGpin goes high. As a
result, the FPGA is configured with the new configuration data stored
in the configuration device. You can add this function to your
programming file (.pof, .jam, .jbc) in the Quartus II software by
enabling the Initiate configuration after programming option in the
Programmer options window (Options menu). This instruction is
also used by the MAX+PLUS II software, .jam files, and .jbc files.
INIT_CONF
00 0110 0001
These instructions are used when programming an EPC2 device
using JTAG ports with a USB-Blaster, MasterBlaster, ByteBlaster II,
EthernetBlaster, or ByteBlasterMV download cable, or using a .jam,
.jbc, or .svf file using an embedded processor.
ISP Instructions
—
f For more information, refer to AN39: IEEE 1149.1 JTAG Boundary-Scan Testing in Altera
Devices.
Configuration Devices for SRAM-Based LUT Devices
January 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
