IEEE Std. 1149.1 (JTAG) Boundary-Scan
You can also program the enhanced configuration devices using the
Quartus II software, the Altera Programming Unit (APU), and the
appropriate configuration device programming adapter. Table 2–11
shows which programming adapter to use with each enhanced
configuration device.
Table 2–11. Table 10. Programming Adapters
Device
Package
Adapter
EPC16
88-pin Ultra FineLine BGA
100-pin PQFP
PLMUEPC-88
PLMQEPC-100
PLMQEPC-100
PLMQEPC-100
EPC8
EPC4
100-pin PQFP
100-pin PQFP
The enhanced configuration device provides JTAG BST circuitry that
complies with the IEEE Std. 1149.1-1990 specification. JTAG boundary-
scan testing can be performed before or after configuration, but not
during configuration.
IEEE Std. 1149.1
(JTAG)
Boundary-Scan
Figure 2–6 shows the timing requirements for the JTAG signals.
Figure 2–6. JTAG Timing Waveforms
TMS
TDI
tJCP
tJCH
tJCL
tJPH
tJPSU
TCK
t
tJPXZ
tJPCO
JPZX
TDO
tJSSU
tJSH
Signal
to Be
Captured
tJSZX
tJSCO
tJSXZ
Signal
to Be
Driven
2–28
Configuration Handbook, Volume 2
Altera Corporation
August 2005
ALTERA [ ALTERA CORPORATION ]
