Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
Table 2–13. Enhanced Configuration Device Configuration Parameters (Part 2 of 2)
Symbol
Parameter
DCLKrising edge to OE
OEassert time to assure reset
EXCLKinput frequency
EXCLKinput period
Condition
Min
60
Typ
Max
Unit
tRE (3)
ns
ns
tLOE
60
fECLK
40% duty cycle
133
MHz
ns
tECLK
7.5
tECLKH
tECLKL
tECLKR
tECLKF
tPOR (4)
EXCLKinput duty cycle high time
EXCLKinput duty cycle low time
EXCLKinput rise time
EXCLKinput fall time
40% duty cycle
40% duty cycle
133 MHz
3.375
3.375
ns
ns
3
3
ns
133 MHz
ns
POR time
2 ms
1
2
3
ms
ms
100 ms
70
100
120
Notes to Table 2–13:
(1) To calculate tOH, use the following equation: tOH = 0.5 (DCLKperiod) - 2.5 ns.
(2) This parameter is used for CRC error detection by the FPGA.
(3) This parameter is used for CONF_DONEerror detection by the enhanced configuration device.
(4) The FPGA VCCINT ramp time should be less than 1-ms for 2-ms POR, and it should be less than 70 ms for 100-ms
POR.
Tables 2–14 through 2–18 provide information on absolute maximum
ratings, recommended operating conditions, DC operating conditions,
supply current values, and pin capacitance data for the enhanced
configuration devices.
Operating
Conditions
Table 2–14. Enhanced Configuration Device Absolute Maximum Rating
Symbol
Parameter
Condition
Min
-0.5
-0.5
Max
4.6
Unit
V
VCC
VI
Supply voltage
With respect to ground
With respect to ground
DC input voltage
3.6
V
IMAX
IOUT
PD
DC VCC or ground current
DC output current, per pin
Power dissipation
100
25
mA
mA
mW
C
-25
360
150
135
135
TSTG
TAMB
TJ
Storage temperature
Ambient temperature
Junction temperature
No bias
-65
-65
Under bias
Under bias
C
C
Altera Corporation
August 2005
2–31
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
