Timing Information
Figure 2–7 shows the configuration timing waveform when using an
enhanced configuration device.
Timing
Information
Figure 2–7. Configuration Timing Waveform Using an Enhanced Configuration Device
nINIT_CONF or
VCC/nCONFIG
tLOE
OE/nSTATUS
nCS/CONF_DONE
tHC
tLC
tCE
(1)
(2)
DCLK
DATA
bit/byte bit/byte
bit/byte
Driven High
1
n
2
tOE
User I/O
User Mode
Tri-State
Tri-State
INIT_DONE
Notes to Figure 2–7:
(1) The enhanced configuration device will drive DCLKlow after configuration.
(2) The enhanced configuration device will DATA[]high after configuration.
Table 2–13 defines the timing parameters when using the enhanced
configuration devices.
f
For flash memory (external flash interface) timing information, please
refer to the corresponding flash data sheet on the Altera web site (Sharp
LHF16J06 for EPC16 devices and Micron MT28F400B3 for EPC4 devices).
Table 2–13. Enhanced Configuration Device Configuration Parameters (Part 1 of 2)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
MHz
ns
fDCLK
tDCLK
tHC
DCLKfrequency
40% duty cycle
66.7
DCLKperiod
15
6
DCLKduty cycle high time
DCLKduty cycle low time
OEto first DCLKdelay
40% duty cycle
40% duty cycle
ns
tLC
6
ns
tCE
40
40
(1)
277
277
ns
tOE
OEto first DATAavailable
DCLKrising edge to DATAchange
OEassert to DCLKdisable delay
OEassert to DATAdisable delay
ns
tOH
ns
tCF (2)
tDF (2)
ns
ns
2–30
Altera Corporation
August 2005
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
