Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
Table 2–12 shows the timing parameters and values for the enhanced
configuration device.
Table 2–12. JTAG Timing Parameters & Values
Symbol Parameter
Min
100
50
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
TCKclock period
tJCH
TCKclock high time
tJCL
TCKclock low time
50
tJPSU
tJPH
JTAG port setup time
20
JTAG port hold time
45
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock output
25
25
25
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
20
45
Capture register hold time
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high-impedance to valid output
Update register valid output to high impedance
25
25
25
Altera Corporation
August 2005
2–29
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
