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EP2C8T144I8N 参数 Datasheet PDF下载

EP2C8T144I8N图片预览
型号: EP2C8T144I8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 470 页 / 5765 K
品牌: ALTERA [ ALTERA CORPORATION ]
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IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices  
If you are testing the device after configuring it, the programmable weak  
pull-up resister or the bus hold feature overrides the CLAMPvalue (the  
value stored in the update register of the boundary-scan cell) at the pin.  
HIGHZ Instruction Mode  
The HIGHZinstruction mode is used to set all of the user I/O pins to an  
inactive drive state. These pins are tri-stated until a new JTAG instruction  
is executed. When this instruction is loaded into the instruction register,  
the bypass register is connected between the TDIand TDOports.  
If you are testing the device after configuring it, the programmable weak  
pull-up resistor or the bus hold feature overrides the HIGHZvalue at the  
pin.  
I/O Voltage Support in JTAG Chain  
A JTAG chain can contain several different devices. However, you should  
be cautious if the chain contains devices that have different VCCIO levels.  
The output voltage level of the TDOpin must meet the specifications of  
the TDIpin it drives. For Cyclone II devices, the TDOpin is powered by  
the VCCIO power supply. Since the VCCIO supply is 3.3 V, the TDOpin  
drives out 3.3 V.  
Devices can interface with each other although they might have different  
VCCIO levels. For example, a device with a 3.3-V TDOpin can drive to a  
device with a 5.0-V TDIpin because 3.3 V meets the minimum TTL-level  
VIH for the 5.0-V TDIpin. JTAG pins on Cyclone II devices can support  
2.5- or 3.3-V input levels.  
f
For more information on MultiVolt I/O support, see the Cyclone II  
Architecture chapter in Volume 1 of the Cyclone II Device Handbook.  
You can also interface the TDIand TDOlines of the devices that have  
different VCCIO levels by inserting a level shifter between the devices. If  
possible, the JTAG chain should be built such that a device with a higher  
VCCIO level drives to a device with an equal or lower VCCIO level. This  
way, a level shifter may be required only to shift the TDOlevel to a level  
acceptable to the JTAG tester. Figure 14–13 shows the JTAG chain of  
mixed voltages and how a level shifter is inserted in the chain.  
Altera Corporation  
February 2007  
14–15  
Cyclone II Device Handbook, Volume 1