PS Configuration
nCONFIGis low and during the beginning of configuration. Once the
optional bit to enable INIT_DONEis programmed into the device (during
the first frame of configuration data), the INIT_DONEpin goes low. When
initialization is complete, the INIT_DONEpin is released and pulled high.
This low-to-high transition signals that the FPGA has entered user mode.
If you do not use the INIT_DONEpin, the initialization period is complete
after the CONF_DONEsignal transitions high and 299 clock cycles are sent
to the CLKUSRpin or after the time tCF2UM (see Table 13–7) if the
Cyclone II device uses the internal oscillator.
After successful configuration, if you intend to synchronize the
initialization of multiple devices that are not in the same configuration
chain, your system must not pull the CONF_DONEsignal low to delay
initialization. Instead, use the optional CLKUSRpin to synchronize the
initialization of multiple devices that are not in the same configuration
chain. Devices in the same configuration chain initialize together if their
CONF_DONEpins are tied together.
1
If the optional CLKUSRpin is being used and nCONFIGis pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSRcontinues toggling during the time
nSTATUSis low (maximum of 40 µs).
User Mode
When initialization is complete, the FPGA enters user mode. In user
mode, the user I/O pins do not have weak pull-up resistors and function
as assigned in your design. Enhanced configuration devices and EPC2
devices drive DCLKlow and DATA0high (EPC1 devices drive the DCLK
pin low and tri-state the DATApin) at the end of configuration.
When the FPGA is in user mode, pull the nCONFIGpin low to begin
reconfiguration. The nCONFIGpin should be low for at least 2 µs. When
nCONFIGtransitions low, the Cyclone II device also pulls the nSTATUS
and CONF_DONEpins low and all I/O pins are tri-stated. Because
CONF_DONEtransitions low, this activates the configuration device since
it will see its nCSpin transition low. Once nCONFIGreturns to a logic high
level and nSTATUSis released by the FPGA, reconfiguration begins.
Error During Configuration
If an error occurs during configuration, the Cyclone II drives its nSTATUS
pin low, resetting itself internally. Since the nSTATUSpin is tied to OE,
the configuration device is also reset. If you turn on the Auto-restart
configuration after error option in the Quartus II software from the
General tab of the Device & Pin Options dialog box, the FPGA
automatically initiates reconfiguration if an error occurs. The Cyclone II
13–36
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
