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EP2C8T144I8N 参数 Datasheet PDF下载

EP2C8T144I8N图片预览
型号: EP2C8T144I8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 470 页 / 5765 K
品牌: ALTERA [ ALTERA CORPORATION ]
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PS Configuration  
f
All information in the “Single Device PS Configuration Using a MAX II  
Device as an External Host” on page 13–22 section is also applicable  
when using a microprocessor as an external host. Refer to that section for  
all configuration information.  
The MicroBlaster™ software driver allows you to configure Altera  
FPGAs, including Cyclone II devices, through the ByteBlaster II or  
ByteBlasterMV cable in PS mode. The MicroBlaster software driver  
supports a RBF programming input file and is targeted for embedded PS  
configuration. The source code is developed for the Windows NT  
operating system, although you can customize it to run on other  
operating systems.  
1
Since the Cyclone II device can decompress the compressed  
configuration data on-the-fly during PS configuration, the  
MicroBlaster software can accept a compressed RBF file as its  
input file.  
f
For more information on the MicroBlaster software driver, see the  
Configuring the MicroBlaster Passive Serial Software Driver White Paper and  
source files on the Altera web site at www.altera.com.  
If you turn on the Enable user-supplied start-up clock (CLKUSR) option  
in the Quartus II software, the Cyclone II devices does not enter user  
mode after the MicroBlaster has transmitted all the configuration data in  
the RBF file. You need to supply enough initialization clock cycles to  
CLKUSRpin to enter user mode.  
Single Device PS Configuration Using a Configuration Device  
You can use an Altera configuration device (for example, an EPC2, EPC1,  
or enhanced configuration device) to configure Cyclone II devices using  
a serial configuration bitstream. Configuration data is stored in the  
configuration device. Figure 13–13 shows the configuration interface  
connections between the Cyclone II device and a configuration device.  
1
The figures in this chapter only show the configuration-related  
pins and the configuration pin connections between the  
configuration device and the FPGA.  
f
For more information on enhanced configuration devices and flash  
interface pins (e.g., PGM[2..0], EXCLK, PORSEL, A[20..0], and  
DQ[15..0]), see the Enhanced Configuration Devices (EPC4, EPC8 &  
EPC16) Data Sheet.  
13–32  
Cyclone II Device Handbook, Volume 1  
Altera Corporation  
February 2007  
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