Configuring Cyclone II Devices
Configuration Stage
When the nSTATUSpin transitions high, the configuration device’s OE
pin also transitions high and the configuration device clocks data out
serially to the FPGA using its internal oscillator. The Cyclone II device
receives configuration data on its DATA0pin and the clock is received on
the DCLKpin. Data is latched into the FPGA on the rising edge of DCLK.
After the FPGA has received all configuration data successfully, it
releases the open-drain CONF_DONEpin, which is pulled high by a pull-
up resistor. Since the Cyclone II device’s CONF_DONEpin is tied to the
configuration device's nCSpin, the configuration device is disabled when
CONF_DONEgoes high. Enhanced configuration and EPC2 devices have
an optional internal pull-up resistor on the nCSpin. You can turn this
option on in the Quartus II software from the General tab of the Device
& Pin Options dialog box. If you do not use this internal pull-up resistor,
you need to connect an external 10-kΩpull-up resistor to the nCSand
CONF_DONEline. A low-to-high transition on CONF_DONEindicates
configuration is complete, and the device can begin initialization.
Initialization Stage
In Cyclone II devices, the default initialization clock source is the
Cyclone II internal oscillator (typically 10 MHz). Cyclone II devices can
also use the optional CLKUSRpin. If your design uses the internal
oscillator, the Cyclone II device supplies itself with enough clock cycles
for proper initialization. The advantage of using the internal oscillator is
you do not need to use another device or source to send additional clock
cycles to the CLKUSRpin during the initialization stage. Additionally, you
can use of the CLKUSRpin as a user I/O pin, which means you have an
additional user I/O pin.
If you want to delay the initialization of the device, you can use the
CLKUSRpin. Using the CLKUSRpin allows you to control when the
Cyclone II device enters user mode. You can delay the Cyclone II devices
from entering user mode for an indefinite amount of time. You can turn
on the Enable user-supplied start-up clock (CLKUSR) option in the
Quartus II software from the General tab of the Device & Pin Options
dialog box. Supplying a clock on CLKUSRdoes not affect the
configuration process. After all configuration data is accepted and
CONF_DONEgoes high, Cyclone II devices require 299 clock cycles to
properly initialize and support a CLKUSRfMAX of 100 MHz.
An optional INIT_DONEpin is available, which signals the end of
initialization and the start of user mode with a low-to-high transition. The
Enable INIT_DONE output option is available in the Quartus II software
from the General tab of the Device & Pin Options dialog box. If you use
the INIT_DONEpin, an external 10-kΩpull-up resistor pulls it high when
Altera Corporation
February 2007
13–35
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
