PS Configuration
Upon power-up, the Cyclone II device goes through a POR. During POR,
the device reset, holds nSTATUSand CONF_DONElow, and tri-states all
user I/O pins. After POR, which typically lasts 100 ms, the Cyclone II
FPGA releases nSTATUSand enters configuration mode when this signal
is pulled high by the external 10-kΩresistor. Once the FPGA successfully
exits POR, all user I/O pins continue to be tri-stated. Cyclone II devices
have weak pull-up resistors on the user I/O pins which are on before and
during configuration.
The configuration device also goes through a POR delay to allow the
power supply to stabilize. The maximum POR time for EPC2 or EPC1
devices is 200 ms. The POR time for enhanced configuration devices can
be set to 100 ms or 2 ms, depending on the enhanced configuration
device’s PORSELpin setting. If the PORSELpin is connected to ground,
the POR delay is 100 ms. If the PORSELpin is connected to VCC, the POR
delay is 2 ms. You must power the Cyclone II device before or during the
enhanced configuration device POR time. During POR, the configuration
device transitions its OEpin low. This low signal delays configuration
because the OEpin is connected to the target device’s nSTATUSpin. When
the target and configuration devices complete POR, they both release the
nSTATUSto OEline, which is then pulled high by a pull-up resistor.
When the power supplies have reached the appropriate operating
voltages, the target FPGA senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration, and initialization.
1
The Cyclone II device does not have a PORSELpin.
Reset Stage
While nCONFIGor nSTATUSis low, the device is in reset. You can delay
configuration by holding the nCONFIGor nSTATUSpin low.
1
VCCINT and VCCIO of the banks where the configuration and
JTAG pins reside need to be fully powered to the appropriate
voltage levels in order to begin the configuration process.
When the nCONFIGsignal goes high, the device comes out of reset and
releases the nSTATUSpin, which is pulled high by a pull-up resistor.
Enhanced configuration and EPC2 devices have an optional internal
pull-up resistor on the OEpin. You can turn on this option in the
Quartus II software from the General tab of the Device & Pin Options
dialog box. If this internal pull-up resistor is not used, you need to
connect an external 10-kΩpull-up resistor to the OEand nSTATUSline.
Once nSTATUSis released, the FPGA is ready to receive configuration
data and the configuration stage begins.
13–34
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
