Introduction to the Stratix GX Device Data Sheet
Figure 1–1. Stratix GX I/O Blocks
DQST9
PLL7
PLL5
9
10
DQST4
PLL11
DQST3
DQST2
Bank 4
DQST8
DQST7
Bank 3
DQST6
DQST5
DQST1
DQST0
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3
VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4
VREF1B2 VREF2B2 VREF3B2 VREF4B2
I/O Bank 13
(5)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins
(3)
Bank 2
(4)
I/O Banks 3, 4, 9 & 10 Support
All Single-Ended I/O Standards
(2)
I/O Bank 14
(5)
PLL1
PLL2
VREF1B1 VREF2B1 VREF3B1 VREF4B1
I/O Banks 1 and 2 Support All
Single-Ended I/O Standards Except
Differential HSTL Output Clocks,
Differential SSTL-2 Output Clocks,
HSTL Class II, GTL, SSTL-18 Class II,
PCI, PCI-X, and AGP 1
×
/2
×
1.5-V PCML
(5)
I/O Bank 17
(5)
Bank 1
(4)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins
(3)
I/O Banks 7, 8, 11 & 12 Support
All Single-Ended I/O Standards
(2)
I/O Bank 16
(5)
I/O Bank 15
(5)
Bank 8
11
DQSB6
DQSB5
12
PLL12
DQSB4
DQSB3
Bank 7
VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7
VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8
PLL8
DQSB9
DQSB8
DQSB7
PLL6
DQSB2
DQSB1
DQSB0
Notes to
(1)
(2)
(3)
(4)
(5)
is a top view of the Stratix GX silicon die.
Banks 9 through 12 are enhanced PLL external clock output banks.
If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the
I/O standards except HSTL class I and II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1×/2×.
For guidelines for placing single-ended I/O pads next to differential I/O pads, see the
Selectable I/O Standards in
Stratix & Stratix GX Devices
chapter of the
Stratix GX Device Handbook, Volume 2.
These I/O banks in Stratix GX devices also support the LVDS, LVPECL, and 3.3-V PCML I/O standards on
reference clocks and receiver input pins (AC coupled).
FPGA Functional
Description
Stratix GX devices contain a two-dimensional row- and column-based
architecture to implement custom logic. A series of column and row
interconnects of varying length and speed provide signal interconnects
between logic array blocks (LABs), memory block structures, and DSP
blocks.
Altera Corporation
February 2005
1–5
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
