High-Speed I/O Interface Functional Description
Table 1–2. Stratix GX Package Options & I/O Pin Counts (Part 2
of 2)
Note (1)
Device
EP1SGX25D
EP1SGX25F
EP1SGX40D
EP1SGX40G
Note to
(1)
The number of I/O pins listed for each package includes dedicated clock pins and
dedicated fast I/O pins. However, these numbers do not include high-speed or
clock reference pins for high-speed I/O standards.
672-Pin FineLine BGA
455
1,020-Pin FineLine BGA
607
607
624
624
Table 1–3. Stratix GX FineLine BGA Package Sizes
Dimension
Pitch (mm)
Area (mm
2
)
Length
×
width (mm
×
mm)
672 Pin
1.00
729
27
×
27
1,020 Pin
1.00
1,089
33
×
33
Table 1–4. Stratix GX Device Speed Grades
Device
EP1SGX10
EP1SGX25
EP1SGX40
672-Pin FineLine BGA
-5, -6, -7
-5, -6, -7
1,020-pin FineLine BGA
-5, -6, -7
-5, -6, -7
High-Speed I/O
Interface
Functional
Description
The Stratix GX device family supports high-speed serial transceiver
blocks with CDR circuitry as well as source-synchronous interfaces. The
channels on the right side of the device use an embedded circuit
dedicated for receiving and transmitting high-speed serial data streams
to and from the system board. These channels are clustered in a
four-channel serial transceiver building block and deliver high-speed
bidirectional point-to-point data transmissions to provide up to
3.1875 Gbps of full-duplex data transmission per channel. The channels
on the left side of the device support source-synchronous data transfers
at up to 1 Gbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport
technology I/O standards.
shows the Stratix GX I/O blocks.
The differential source-synchronous serial interface and the high-speed
serial interface are described in the
Stratix GX Transceivers
chapter of the
Stratix GX Device Handbook, Volume 1.
1–4
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005
ALTERA [ ALTERA CORPORATION ]
