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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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1. Introduction to the  
Stratix GX Device Data Sheet  
SGX51001-1.0  
The Stratix® GX family of devices is Altera’s second FPGA family to  
combine high-speed serial transceivers with a scalable, high-performance  
logic array. Stratix GX devices include 4 to 20 high-speed transceiver  
channels, each incorporating clock data recovery (CDR) technology and  
embedded SERDES capability at data rates of up to 3.1875 gigabits per  
second (Gbps). These transceivers are grouped by four-channel  
transceiver blocks, and are designed for low power consumption and  
small die size. The Stratix GX FPGA technology is built upon the Stratix  
architecture, and offers a 1.5-V logic array with unmatched performance,  
flexibility, and time-to-market capabilities. This scalable,  
Overview  
high-performance architecture makes Stratix GX devices ideal for  
high-speed backplane interface, chip-to-chip, and communications  
protocol-bridging applications.  
Transceiver block features are as follows:  
Features  
High-speed serial transceiver channels with CDR provides  
500-megabits per second (Mbps) to 3.1875-Gbps full-duplex  
operation  
Devices are available with 4, 8, 16, or 20 high-speed serial  
transceiver channels providing up to 127.5 Gbps of full-duplex  
serial bandwidth  
Support for transceiver-based protocols, including 10 Gigabit  
Ethernet attachment unit interface (XAUI), Gigabit Ethernet  
(GigE), and SONET/SDH  
Compatible with PCI Express, SMPTE 292M, Fibre Channel, and  
Serial RapidIO I/O standards  
Programmable differential output voltage (VOD), pre-emphasis,  
and equalization settings for improved signal integrity  
Individual transmitter and receiver channel power-down  
capability implemented automatically by the Quartus® II  
software for reduced power consumption during non-operation  
Programmable transceiver-to-FPGA interface with support for  
8-, 10-, 16-, and 20-bit wide data paths  
1.5-V pseudo current mode logic (PCML) for 500 Mbps to  
3.1875 Gbps  
Support for LVDS, LVPECL, and 3.3-V PCML on reference  
clocks and receiver input pins (AC-coupled)  
Built-in self test (BIST)  
Hot insertion/removal protection circuitry  
Altera Corporation  
February 2005  
1–1  
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