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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Introduction to the Stratix GX Device Data Sheet
Figure 1–2. Stratix GX Block Diagram
M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
M4K RAM Blocks
for True Dual-Port
Memory & Other Embedded
Memory Functions
IOEs Support DDR, PCI, GTL+, SSTL-3,
SSTL-2, HSTL, LVDS, LVPECL, PCML,
HyperTransport & other I/O Standards
IOEs
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M-RAM Block
LABs
DSP
Block
The number of M512 RAM, M4K RAM, and DSP blocks varies by device
along with row and column numbers and M-RAM blocks.
lists
the resources available in Stratix GX devices.
Table 1–5. Stratix GX Device Resources
Device
EP1SGX10
EP1SGX25
EP1SGX40
M512 RAM
M4K RAM
Columns/Blocks Columns/Blocks
4 / 94
6 / 224
8 / 384
2 / 60
3 / 138
3 / 183
M-RAM
Blocks
1
2
4
DSP Block
Columns/Blocks
2/6
2 / 10
2 / 14
LAB
Columns
40
62
77
LAB Rows
30
46
61
Altera Corporation
February 2005
1–7
Stratix GX Device Handbook, Volume 1