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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Features  
Pattern detector and word aligner supports programmable  
patterns  
8B/10B encoder/decoder performs 8- to 10-bit encoding and 10-  
to 8-bit decoding  
Rate matcher compliant with IEEE 802.3-2002 for GigE mode  
and with IEEE 802-3ae for XAUI mode  
Channel bonding compliant with IEEE 802.3ae (for XAUI mode  
only)  
Device can bypass some transceiver block features if necessary  
FPGA features are as follows:  
10,570 to 41,250 logic elements (LEs); see Table 1–1  
Up to 3,423,744 RAM bits (427,968 bytes) available without  
reducing logic resources  
TriMatrixmemory consisting of three RAM block sizes to  
implement true dual-port memory and first-in-out (FIFO)  
buffers  
Up to 16 global clock networks with up to 22 regional clock  
networks per device region  
High-speed DSP blocks provide dedicated implementation of  
multipliers (faster than 300 MHz), multiply-accumulate  
functions, and finite impulse response (FIR) filters  
Up to eight general usage phase-locked loops (four enhanced  
PLLs and four fast PLLs) per device provide spread spectrum,  
programmable bandwidth, clock switchover, real-time PLL  
reconfiguration, and advanced multiplication and phase  
shifting  
Support for numerous single-ended and differential I/O  
standards  
High-speed source-synchronous differential I/O support on up  
to 45 channels for 1-Gbps performance  
Support for source-synchronous bus standards, including  
10-Gigabit Ethernet XSBI, Parallel RapidIO, UTOPIA IV,  
Network Packet Streaming Interface (NPSI), HyperTransport  
TM  
technology, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4  
Support for high-speed external memory, including zero bus  
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII)  
SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM  
(FCRAM), and single data rate (SDR) SDRAM  
Support for multiple intellectual property megafunctions from  
Altera® MegaCore® functions and Altera Megafunction Partners  
SM  
Program (AMPP ) megafunctions  
Support for remote configuration updates  
Dynamic phase alignment on LVDS receiver channels  
1–2  
Stratix GX Device Handbook, Volume 1  
Altera Corporation  
February 2005  
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