Figure 2–27. EP1SGX40G Device Inter-Transceiver & Global Clock Connections
Note (1)
Transceiver Block 0
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
TX PLL
refclkb
/2
IQ2
4
4
Global Clks, I/O Bus, Gen Routing
Receiver
PLLs
Transceiver Block 1
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
IQ0
IQ1
IQ2
TX PLL
refclkb
/2
(2)
IQ2
4
4
Global Clks, I/O Bus, Gen Routing
Receiver
PLLs
PLD
Global
Clocks
Transceiver Block 4
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
TX PLL
refclkb
16
/2
4
IQ2
4
Global Clks, I/O Bus, Gen Routing
Receiver
PLLs
Transceiver Block 2
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
TX PLL
refclkb
/2
(2)
IQ2
4
Global Clks, I/O Bus, Gen Routing
4
Receiver
PLLs
Transceiver Block 3
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
TX PLL
refclkb
/2
(2)
IQ2
4
4
Global Clks, I/O Bus, Gen Routing
Receiver
PLLS
Notes to Figure 2–27:
(1) IQ lines are inter-transceiver block lines.
(2) If the /2 pre-divider is used, the path to drive the PLD logic array, local, or global clocks is not allowed.
(3) There are four receiver PLLs in each transceiver block.
2–32
Altera Corporation
June 2006
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
