Table 2–9. BIST Data Output & Verifier Alignment Pattern (Part 2 of 2)
BIST Mode
PRBS 16-bit
PRBS 20-bit
Output
Polynomials
Verifier Word Alignment Pattern
1000000011111111
1111111111
28 – 1
x8 + x7 + x5 + x3 + 1
x10 + x7 + 1
210 – 1
Incremental 10-bit K28.5, K27.7, Data (00-FF
incremental), K28.0, K28.1,
0101111100 (K28.5)
K28.2, K28.3, K28.4, K28.6,
K28.7, K23.7, K30.7, K29.7 (1)
Incremental 20-bit K28.5, K27.7, Data (00-FF
incremental), K28.0, K28.1,
0101111100 (K28.5)
K28.2, K28.3, K28.4, K28.6,
K28.7, K23.7, K30.7, K29.7 (1)
High frequency
Low frequency
Mixed frequency
1010101010
0011111000
0011111010 or 1100000101
Note to Table 2–9:
(1) This output repeats.
Stratix GX Clocking
The Stratix GX global clock can be driven by certain REFCLKBpins, all
transmitter PLL outputs, and all receiver PLL outputs. The REFCLKBpins
(except for transceiver block 0 and transceiver block 4) can drive inter-
transceiver and global clock lines as well as feed the transmitter and
receiver PLLs. The output of the transmitter PLL can only feed global
clock lines and the reference clock port of the receiver PLL.
Figures 2–26 and 2–27 are diagrams of the Inter-Transceiver line
connections as well as the global clock connections for the EP1SGX25F
and EP1SGX40G devices. For devices with fewer transceivers, ignore the
information about the unavailable transceiver blocks.
2–30
Altera Corporation
Stratix GX Device Handbook, Volume 1
June 2006
ALTERA [ ALTERA CORPORATION ]
