Stratix GX Transceivers
Figure 2–26. EP1SGX25F Device Inter-Transceiver & Global Clock Connections
Note (1)
Transceiver Block 0
IQ0
IQ1
Transmitter
PLL
Global Clocks, I/O Bus, General Routing
refclkb
/2
IQ2
4
4
Global Clocks, I/O Bus, General Routing
Receiver
PLLs
IQ0
IQ1
IQ2
Transceiver Block 1
IQ0
IQ1
Transmitter
PLL
Global Clocks, I/O Bus, General Routing
refclkb
/2
(2)
IQ2
4
4
Global Clocks, I/O Bus, General Routing
Receiver
PLLs
16
Transceiver Block 2
PLD Global Clocks
IQ0
IQ1
Transmitter
PLL
Global Clocks, I/O Bus, General Routing
refclkb
/2
(2)
IQ2
4
4
Global Clocks, I/O Bus, General Routing
Receiver
PLLs
Transceiver Block 3
IQ0
IQ1
Transmitter
PLL
Global Clocks, I/O Bus, General Routing
refclkb
/2
(2)
IQ2
4
4
Global Clocks, I/O Bus, General Routing
Receiver
PLLs
Notes to Figure 2–26:
(1) IQ lines are inter-transceiver block lines.
(2) If the /2 pre-divider is used, the path to drive the PLD logic array, local, or global clocks is not allowed.
(3) There are four receiver PLLs in each transceiver block.
Altera Corporation
June 2006
2–31
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
