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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix GX Architecture  
Programmable delays can increase the register-to-pin delays for output  
and/or output enable registers. A programmable delay exists to increase  
the tZX delay to the output pin, which is required for ZBT interfaces.  
Table 4–21 shows the programmable delays for Stratix GX devices.  
Table 4–21. Stratix GX Programmable Delay Chain  
Programmable Delays  
Quartus II Logic Option  
Input pin to logic array delay  
Input pin to input register delay  
Output pin delay  
Decrease input delay to internal cells  
Decrease input delay to input register  
Increase delay to output pin  
Output enable register tCO delay  
Output tZX delay  
Increase delay to output enable pin  
Increase tZX delay to output pin  
Increase output clock enable delay  
Increase input clock enable delay  
Output clock enable delay  
Input clock enable delay  
Logic array to output register delay Decrease input delay to output register  
Output enable clock enable delay Increase output enable clock enable delay  
The IOE registers in Stratix GX devices share the same source for clear or  
preset. You can program preset or clear for each individual IOE. You can  
also program the registers to power up high or low after configuration is  
complete. If programmed to power up low, an asynchronous clear can  
control the registers. If programmed to power up high, an asynchronous  
preset can control the registers. This feature prevents the inadvertent  
activation of another device’s active-low input upon power-up. If one  
register in an IOE uses a preset or clear signal then all registers in the IOE  
must use that same signal if they require preset or clear. Additionally, a  
synchronous reset signal is available for the IOE registers.  
Double-Data Rate I/O Pins  
Stratix GX devices have six registers in the IOE, which support DDR  
interfacing by clocking data on both positive and negative clock edges.  
The IOEs in Stratix GX devices support DDR inputs, DDR outputs, and  
bidirectional DDR modes.  
Altera Corporation  
February 2005  
4–103  
Stratix GX Device Handbook, Volume 1  
 
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