5. Configuration & Testing
SGX51005-1.0
Stratix® GX devices feature the SignalTap® embedded logic analyzer,
which monitors design operation over a period of time through the
IEEE Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed
without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA®
packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.
SignalTap
Embedded Logic
Analyzer
The logic, circuitry, and interconnects in the Stratix GX architecture are
configured with CMOS SRAM elements. Stratix GX devices are
reconfigurable and are 100% tested prior to shipment. As a result, you do
not have to generate test vectors for fault coverage purposes, and can
instead focus on simulation and design verification. In addition, you do
not need to manage inventories of different ASIC designs. Stratix GX
devices can be configured on the board for the specific functionality
required.
Configuration
Stratix GX devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers in-system programmability (ISP)-capable configuration
devices that configure Stratix GX devices via a serial data stream.
Stratix GX devices can be configured in under 100 ms using 8-bit parallel
data at 100 MHz. The Stratix GX device’s optimized interface allows
microprocessors to configure it serially or in parallel, and synchronously
or asynchronously. The interface also enables microprocessors to treat
Stratix GX devices as memory and configure them by writing to a virtual
memory location, making reconfiguration easy. After a Stratix GX device
has been configured, it can be reconfigured in-circuit by resetting the
device and loading new data. Real-time changes can be made during
system operation, enabling innovative reconfigurable computing
applications.
Operating Modes
The Stratix GX architecture uses SRAM configuration elements that
require configuration data to be loaded each time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power up,
Altera Corporation
February 2005
5–1
ALTERA [ ALTERA CORPORATION ]
