Stratix GX Architecture
Table 4–33. Stratix GX JTAG Instructions (Part 2 of 2)
JTAG Instruction
Description
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation while holding I/O pins to a state defined by the data in the boundary-scan
register.
CLAMP(1)
Used when configuring a Stratix GX device through the JTAG port with a MasterBlasterTM
or ByteBlasterMVTM download cable, or when using a .jamfile or .jbcfile with an
embedded processor.
ICR instructions
PULSE_NCONFIG Emulates pulsing the nCONFIGpin low to trigger reconfiguration even though the physical
pin is unaffected.
Allows the IOE standards to be configured through the JTAG chain. Stops configuration if
executed during configuration. Can be executed before or after configuration.
CONFIG_IO
SignalTap
Monitors internal device operation with the SignalTap embedded logic analyzer.
instructions
Note to Table 4–33:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
The Stratix GX device instruction register length is 10 bits, and the
USERCODE register length is 32 bits. Tables 4–34 and 4–35 show the
boundary-scan register length and IDCODE information for Stratix GX
devices.
Table 4–34. Stratix GX Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EP1SGX10
EP1SGX25
EP1SGX40
1,029
1,665
1,941
Table 4–35. 32-Bit Stratix GX Device IDCODE (Part 1 of 2)
IDCODE (32 Bits) (1)
Device
Manufacturer Identity
Version (4 Bits)
Part Number (16 Bits)
LSB (1 Bit) (2)
(11 Bits)
EP1SGX10
EP1SGX25
0000
0000
0010 0000 0100 0001
0010 0000 0100 0011
000 0110 1110
000 0110 1110
1
1
Altera Corporation
February 2005
4–123
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
