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EP1SGX40GF1020I6N 参数 Datasheet PDF下载

EP1SGX40GF1020I6N图片预览
型号: EP1SGX40GF1020I6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 279 页 / 3682 K
品牌: ALTERA [ ALTERA CORPORATION ]
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IEEE Std. 1149.1 (JTAG) Boundary-Scan Support  
Table 4–35. 32-Bit Stratix GX Device IDCODE (Part 2 of 2)  
IDCODE (32 Bits) (1)  
Device  
Manufacturer Identity  
(11 Bits)  
Version (4 Bits)  
Part Number (16 Bits)  
LSB (1 Bit) (2)  
EP1SGX40  
0000  
0010 0000 0100 0101  
000 0110 1110  
1
Notes to Table 4–35:  
(1) The most significant bit (MSB) is at the left end of the string.  
(2) The IDCODE’s least significant bit (LSB) is always 1.  
Figure 4–72 shows the timing requirements for the JTAG signals.  
Figure 4–72. Stratix GX JTAG Waveforms  
TMS  
TDI  
tJCP  
tJCH  
t JCL  
tJPH  
tJPSU  
TCK  
TDO  
tJPXZ  
tJPZX  
tJPCO  
tJSSU  
tJSH  
Signal  
to Be  
Captured  
tJSCO  
tJSZX  
tJSXZ  
Signal  
to Be  
Driven  
Table 4–36 shows the JTAG timing parameters and values for Stratix GX  
devices.  
Table 4–36. Stratix GX JTAG Timing Parameters & Values (Part 1 of 2)  
Symbol  
tJCP  
Parameter  
Min (ns) Max (ns)  
100  
50  
TCKclock period  
tJCH  
TCKclock high time  
TCKclock low time  
JTAG port setup time  
tJCL  
50  
tJPSU  
20  
4–124  
Stratix GX Device Handbook, Volume 1  
Altera Corporation  
February 2005  
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