Stratix Architecture
Table 2–9. M-RAM Block Configurations (True Dual-Port)
Port B
16K × 36
Port A
64K × 9
v
32K × 18
v
8K × 72
v
64K × 9
32K × 18
16K × 36
8K × 72
v
v
v
v
v
v
v
v
v
v
v
v
v
The read and write operation of the memory is controlled by the WREN
signal, which sets the ports into either read or write modes. There is no
separate read enable (RE) signal.
Writing into RAM is controlled by both the WRENand byte enable
(byteena) signals for each port. The default value for the byteena
signal is high, in which case writing is controlled only by the WRENsignal.
The byte enables are available for the ×18, ×36, and ×72 modes. In the
×144 simple dual-port mode, the two sets of byteenasignals
(byteena_aand byteena_b) are combined to form the necessary
16 byte enables. Tables 2–10 and 2–11 summarize the byte selection.
Table 2–10. Byte Enable for M-RAM Blocks Notes (1), (2)
byteena[3..0]
datain ×18
datain ×36
datain ×72
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[4] = 1
[5] = 1
[6] = 1
[7] = 1
[8..0]
[8..0]
[8..0]
[17..9]
[17..9]
[17..9]
–
–
–
–
–
–
[26..18]
[26..18]
[35..27]
[44..36]
[53..45]
[62..54]
[71..63]
[35..27]
–
–
–
–
Altera Corporation
July 2005
2–35
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
